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1 of 17 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds1254 is a fully nonvolatile static ram (nv sram) (organized as 2m words by 8 bits) with built-in real-time clock. it has a self-contained lithium energy source and control circuitry that constantly monitors v cc for an out-of- tolerance condition. when such a condition occurs, the ds1254 makes use of an attached ds3800 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. additionally, the ds1254 has dedicated circuitry for monitoring the status of an attached ds3800 battery cap. features ? real-time clock (rtc) keeps track of hundredths of seconds, seconds, minutes, hours, days, date, months, and years with automatic leap-year compensation valid up to the year 2100 ? 2m x 8 nv sram ? watch function is transparent to ram operation ? automatic data protection during power loss ? unlimited write-cycle endurance ? surface-mountable bga module construction ? over 10 years of data retention in the absence of power ? battery monitor checks remaining capacity daily ? +3.3v operation ? underwriters laboratory (ul) recognized ( www.maxim-ic.com/qa/info/ul/ ) applications telecom switches routers raid systems package outline typical operating circuit ordering information part temp range pin-package voltage range (v) top mark ds1254wb-150 0c to +70c 40mm bga 3.3 ds1254w-150 DS1254WB2-150 0c to +70c 40mm bga 3.3 ds1254w-150 ds1254 2m x 8 nv sram with phantom clock www.maxim-ic.com side -a- shown (for reference only, not to scale) component placement may vary. 19-4621; 12/09 +3.3v downloaded from: http:///
ds1254 2 of 17 detailed description the ds1254 is a fully nonvolatile static ram (nv sram) (o rganized as 2m words by 8 bits) with built-in real-time clock. it has a self-contained lithium energy source and control circuitry that constantly monitors v cc for an out-of- tolerance condition. when such a condition occurs, the ds1254 makes use of an attached ds3800 battery cap to maintain clock information and preserve stored data while pr otecting that data by disall owing all memory accesses. additionally, the ds1254 has dedicated circuitry for monitoring the status of an attached ds3800 battery cap. the phantom clock provides timekeeping information incl uding hundredths of seconds, seconds, minutes, hours, day, date, month, and year info rmation. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. t he phantom clock operates in either 24-hour or 12-hour format with an am/pm indicator. because the ds1254 has a total of 168 balls and only 35 active signals, balls are wired together into groups, thus providing redundant connections for every signal. figure 1. pin configuration v cc a7 a6 a5 gnd a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 2928 27 26 25 24 23 22 21 10 11 12 13 14 15 16 17 18 19 20 4140 39 38 37 36 35 34 33 32 31 30 v cc a 17 a 18 a 19 gnd a 20 ce oe we a0 dq0dq1 dq2 dq3 gnd dq4dq5 dq6 dq7 bw v cc a8 a9 a10 a11 gnd a12 a13 a14 a15 a16 v cc receptacles for ds3800 battery cap pins gnd v bat dallas semiconductor ds1254 downloaded from: http:///
ds1254 3 of 17 ram read mode the ds1254 executes a read cycle whenever we is inactive (high) and ce is active (low). the unique address specified by the 21 address inputs (a0Ca 20) defines which of the 2mb of data is to be accessed. valid data will be available to the eight data-output drivers within t acc (access time) after the last address input is stable, providing that ce and oe access times and states are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later occurring signal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. ram write mode the ds1254 is in the write mode whenever we and ce are in their active (low) state after address inputs are stable. the later occurring falling edge of ce or we will determine the start of the wr ite cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycl es to avoid bus contention. however, if the output bus has been enabled ( ce and oe active), then we will disable the outputs in t odw from its falling edge. data retention mode the device is fully accessible and data can be written and read only when v cc is greater than v pf . however, when v cc falls below the power-fail point, v pf (point at which write protection occu rs), the internal clock registers and sram are blocked from any access. when v cc falls below v bat , device power is switched from the v cc to v bat . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. all signals must be powered down when v cc is powered down. phantom clock operation communication with the phantom clock is established by patte rn recognition on a serial bit stream of 64 bits that must be matched by executing 64 consec utive write cycles contai ning the proper data on dq0. all accesses that occur prior to recognition of the 64-bit pattern are directed to memory. after recognition is established, the next 64 read or write cycles either extrac t or update data in the phantom clock, and memory access is inhibited. data transfer to and from the timekeeping function is acco mplished with a serial bit stream under control of chip enable ( ce ), output enable ( oe ), and write enable ( we ). initially, a read cycle to any memory location using the ce and oe control of the phantom clock starts the pattern-recogniti on sequence by moving a pointer to the first bit of the 64-bit comparison register. next, 64 cons ecutive write cycles are executed using the ce and we signals of the device. these 64 write cycles are used only to gain access to the phantom clock. therefor e, any address within the first 512kb of memory, (00h to 7ffffh) is acceptable. ho wever, the write cycles generated to gain access to the phantom clock are also writing data to a location in the me mory. the preferred way to manage this requirement is to set aside just one address location in memory as a phantom clock scratch pad. when the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. if a match is found, the pointer increments to the next location of the comparison regist er and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored . if a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the co mparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as described abov e until all the bits in the comparison register have been matched (this bit pattern is shown in figure 2). with a correct match for 64-bits, the phantom clock is enabled and downloaded from: http:///
ds1254 4 of 17 data transfer to or from the timekeeping registers can proceed. the next 64 cycles will cause the phantom clock to either receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern-recognition sequence or data-transfer sequence to the phantom clock. phantom clock regist er information the phantom clock information is contai ned in eight registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern-recognition sequence has been completed. when updating the phantom clock registers, each register must be handled in groups of 8 bits. writing and reading individual bits within a register could produce erroneous results. these read/ write registers are defined in figure 3. figure 2. phantom clock protocol definition note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a3, 5c . the odds of this pattern being accidentally duplicated and causing inadvertent entry to the ph antom clock is less than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb. downloaded from: http:///
ds1254 5 of 17 figure 3. phantom clock register definition downloaded from: http:///
ds1254 6 of 17 am/pm/12/24 mode bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20C23 hours). oscillator bit bit 5 of the day register controls the o scillator. when set to logic 1, the oscillator is off. when set to logic 0, the oscillator turns on and the watch beco mes operational. zero bits registers 1, 2, 3, 4, 5, and 6 contain one or more bits that will always read logic 0. when writing these locations, either a logic 1 or logic 0 is acceptable. battery monitoring the ds1254 automatically monitors the battery in an attach ed ds3800 battery cap on a 24-hour time interval. such monitoring begins within t rec after v cc rises above v pf and is suspended when power failure occurs. after each 24-hour period has elapsed, the battery is connected to an internal 1m ? test resistor for one second. during this one second, if the battery voltage falls below t he battery-voltage trip point (~2.6v), the battery warning output bw is asserted. once asserted, bw remains active until the attached ds3800 battery cap is replaced. however, the battery is still retested after each v cc power-up, even if it was active on power-down. if the battery voltage is found to be higher than ~2.6v during such testing, bw is de-asserted and regular testing resumes. bw has an open-drain output driver. downloaded from: http:///
ds1254 7 of 17 absolute maxi mum ratings voltage range on any pin relative to ground -0.3v to +4.6v operating temperature range 0 ? c to +70 ? c storage temperature range -40 ? c to +70 ? c soldering temperature see ipc/jedec j-std-020 stresses beyond those listed under absolute maximum ratings may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rati ng conditions for extended peri ods may affect device. recommended dc operating conditions (t a = 0 ? c to +70 ? c) parameter symbol conditions min typ max units notes power-supply voltage v cc 3.0 3.3 3.7 v 1 logic 1 voltage (all inputs) v ih 2.0 v cc + 0.3 v 1 logic 0 voltage (all inputs) v il -0.3 0.6 v 1 dc electrical characteristics (v cc = 3.3v ? 10 % , t a = 0 ? c to +70 ? c.) parameter symbol min typ max units notes input leakage current i il -4.0 +4.0 ? a i/o leakage current i io -4.0 +4.0 ? a output current at 2.4v i oh -1.0 ma 3 output current at 0.4v i ol 2.0 ma 3 standby current ( ce = 2.2v) i ccs1 5.0 7 ma standby current ( ce = v cc - 0.5v) i ccs2 2.0 3.0 ma operating current, t cyc = 100ns i cco1 50 ma write protection voltage v pf 2.8 2.97 v 1 capacitance (t a = +25 ? c) parameter symbol min typ max units notes input capacitance: a0 to a18, oe , we , ce c in 25 50 pf input capacitance: a19 to a20 c in 5 10 pf i/o capacitance: dq0 to dq7 c io 25 50 pf output capacitance: bw c out 5 10 pf downloaded from: http:///
ds1254 8 of 17 ac electrical characteristics (v cc = 3.3v ? 10%, t a = 0 ? c to +70 ? c.) parameter symbol min max units notes read cycle time t rc 150 ns address access time t aac 150 ns oe to output valid t oe 75 ns ce to output valid t co 150 ns ce or oe to output active t coe 0 ns 2 output high-z from deselection t od 70 ns 2 output hold from address change t oh 5 ns write cycle time t wc 150 ns we , ce pulse width t wp 100 ns 5 address setup time t aw 10 ns t ah1 5 ns 6 address hold time t ah2 25 ns 7 output high-z from we t odw 70 ns 2 output active from we t oew 5 ns 2 data setup time t ds 60 ns 8 t dh1 0 ns 6 data hold time t dh2 20 ns 8 read recovery (clock access only) t rr 20 ns write recovery (clock access only) t wr 20 ns power-up/power-down characteristics (v cc = 3.3v ? 10%) parameter symbol min typ max units notes ce and we at v ih before power-down t pd 0 ? s v cc fall time: v pf(max) to v pf(min) t f 300 ? s v cc fall time: v pf(min) to v bat t fb 10 ? s v cc rise time: 0v to v pf(min) t r 150 ? s v cc valid to end of write protection t rec 125 ms v cc valid to bw valid t bpu 1 s 3 (t a = +25 ? c) parameter symbol min typ max units notes expected data-retention time (oscillator on) t dr 10 years 4 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. downloaded from: http:///
ds1254 9 of 17 battery warning timing (v cc = 3.3v ? 10%, t a = 0 ? c to +70 ? c) parameter symbol min typ max units notes battery test cycle t btc 24 hour battery test pulse width t btpw 1 seconds battery test to bw active t bw 1 seconds v cc valid to bw valid t bpu 1 seconds 3 ac test conditions output load: 100pf + 1 ttl gate input pulse levels: 0v to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns figure 4. memory read cycle timing (note 9) t rc address t acc ce oe dq0Cdq7 t oh t co t oe t coe t coe t od t od output data valid downloaded from: http:///
ds1254 10 of 17 figure 5. memory write cycle ti ming, write-enable controlled (notes 5, 6, 8, 10, 11, 12, and 13) figure 6. memory write cycle timing, chip-enable controlled (notes 5, 7, 8, 10, 11, 12, and 13) t wc t ah1 t aw t oew t ds data in stable t dh1 t odw t wp address ce we dq0Cdq7 t wc t ah2 t aw t ds t dh2 t coe t odw t wp address ce we dq0Cdq7 data in stable downloaded from: http:///
ds1254 11 of 17 figure 7. read cycle to phantom clock figure 8. write cycle to phantom clock t rc ce oe dq0 t co t oe t coe t coe t od t od output data valid t rr we = v ih t wc t wr t ds t dh1 t wp we ce dq0 data in stable t wp oe = v ih t dh2 t ah2 downloaded from: http:///
ds1254 12 of 17 figure 9. power-up/power-dow n waveform timing (note 14) v cc v pf(max) v pf(min) t f t fb t pd t dr v bat t rec t bpu slews with v cc bw t r slews with v cc ce we , figure 10. battery warni ng detection (note 3) battery test active bw v cc v bat t bpu 2.6v t btc t btpw t bw downloaded from: http:///
ds1254 13 of 17 notes: 1) voltage referenced to ground. 2) these parameters are sampled with a 50pf load and are not 100% tested. 3) bw is an open-drain output and, as such, cannot source current. an external pullup resistor should be connected to this pin for proper operation. bw can sink 10ma. 4) the ds3800 battery cap is a one-time use part, but c an be removed and replaced. by design, ds3800 removal will mechanically damage the battery cap, which eliminates the accidental use of a previously attached and possibly low-capacity battery cap. 5) t wp specified as the logical and of ce and we , t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 6) t ah1 , t dh1 are measured from we going high. 7) t ah2 , t dh2 are measured from ce going high. 8) t ds is measured from the earlier of ce or we going high. 9) we is high for a read cycle. 10) oe = v ih or v il . if oe = v ih during write cycle, the output buffe rs remain in a high-impedance state. 11) if the ce low transition occurs simultaneously with or later than the we low transition in a write-enable- controlled write cycle, the output buffers remain in a high-impedance state during this period. 12) if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high-impedance state during this period. 13) if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high-impedance state during this period. 14) in a power-down condition, the voltage on any pin cannot exceed the voltage on v cc . downloaded from: http:///
ds1254 14 of 17 package information (the package drawing(s) in this data s heet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) pkg min max a in mm 1.570 39.88 1.580 40.13 b in mm 1.570 39.88 1.580 40.13 c in mm 0.033 0.84 0.043 1.09 d in mm 1.497 38.02 1.503 38.18 e in mm 0.047 1.19 0.053 1.35 f in mm 0.033 0.84 0.043 1.09 g in mm 0.047 1.19 0.053 1.35 h in mm 0.234 5.94 0.240 6.10 i in mm 0.160 4.00 0.200 5.10 k in mm 0.025 0.64 0.032 0.82 downloaded from: http:///
ds1254 15 of 17 package information (continued) (the package drawing(s) in this data s heet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) ds1254 with attached ds3800 battery cap pkg min max a in mm 1.656 42.06 1.668 42.37 b in mm 1.656 42.06 1.668 42.37 c in mm 0.485 12.32 downloaded from: http:///
ds1254 16 of 17 package information (continued) (the package drawing(s) in this data s heet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) recommended land pattern (wit h overlaid package outline) the ds1254 bga is a subset of the industry-standard 40mm bga format, with all balls on a 50-mil grid. corner balls have been removed to provide space for the electric al and mechanical interface features that facilitate attachment of the ds3800 battery cap. 0.150 0.250 0.500 note note: ground shield to isolate rtc xtal from emi. downloaded from: http:///
ds1254 17 of 17 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered tradema rk of maxim integrated products, inc. revision history revision date description pages changed 5/09 changed t awmin = 0ns to t awmin = 10ns in the electrical characteristics table. 8, 9 12/09 removed the ds1254yb ordering information and 5v operational characteristics. 1, 7C10 downloaded from: http:///

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